/*!
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\file drv_usb_host.c
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\brief USB host mode low level driver
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\version 2020-08-01, V3.0.0, firmware for GD32F30x
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "drv_usb_hw.h"
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#include "drv_usb_core.h"
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#include "drv_usb_host.h"
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const uint32_t PIPE_DPID[2] = {
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PIPE_DPID_DATA0,
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PIPE_DPID_DATA1
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};
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/*!
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\brief initializes USB core for host mode
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\param[in] pudev: pointer to selected usb host
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\param[out] none
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\retval operation status
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*/
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usb_status usb_host_init (usb_core_driver *pudev)
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{
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uint32_t i = 0U, inten = 0U;
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uint32_t nptxfifolen = 0U;
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uint32_t ptxfifolen = 0U;
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/* restart the PHY Clock */
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*pudev->regs.PWRCLKCTL = 0U;
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/* support FS/LS only */
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pudev->regs.hr->HCTL &= ~HCTL_SPDFSLS;
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/* configure data FIFOs size */
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#ifdef USB_FS_CORE
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if (USB_CORE_ENUM_FS == pudev->bp.core_enum) {
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/* set Rx FIFO size */
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pudev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE;
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/* set non-periodic Tx FIFO size and address */
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nptxfifolen |= USB_RX_FIFO_FS_SIZE;
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nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U;
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pudev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen;
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/* set periodic Tx FIFO size and address */
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ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_NPFIFO_FS_SIZE;
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ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U;
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pudev->regs.gr->HPTFLEN = ptxfifolen;
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}
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#endif /* USB_FS_CORE */
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#ifdef USE_OTG_MODE
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/* clear host set hnp enable in the usb_otg control register */
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pudev->regs.gr->GOTGCS &= ~GOTGCS_HHNPEN;
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#endif /* USE_OTG_MODE */
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/* make sure the FIFOs are flushed */
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/* flush all Tx FIFOs in device or host mode */
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usb_txfifo_flush (&pudev->regs, 0x10U);
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/* flush the entire Rx FIFO */
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usb_rxfifo_flush (&pudev->regs);
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/* disable all interrupts */
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pudev->regs.gr->GINTEN = 0U;
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/* clear any pending USB OTG interrupts */
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pudev->regs.gr->GOTGINTF = 0xFFFFFFFFU;
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/* enable the USB wakeup and suspend interrupts */
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pudev->regs.gr->GINTF = 0xBFFFFFFFU;
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/* clear all pending host channel interrupts */
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for (i = 0U; i < pudev->bp.num_pipe; i++) {
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pudev->regs.pr[i]->HCHINTF = 0xFFFFFFFFU;
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pudev->regs.pr[i]->HCHINTEN = 0U;
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}
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#ifndef USE_OTG_MODE
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usb_portvbus_switch (pudev, 1U);
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#endif /* USE_OTG_MODE */
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pudev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
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/* enable host_mode-related interrupts */
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if (USB_USE_FIFO == pudev->bp.transfer_mode) {
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inten = GINTEN_RXFNEIE;
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}
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inten |= GINTEN_SESIE | GINTEN_HPIE | GINTEN_HCIE | GINTEN_ISOINCIE;
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pudev->regs.gr->GINTEN |= inten;
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inten = GINTEN_DISCIE | GINTEN_SOFIE;
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pudev->regs.gr->GINTEN &= ~inten;
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return USB_OK;
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}
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/*!
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\brief control the VBUS to power
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\param[in] pudev: pointer to selected usb host
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\param[in] state: VBUS state
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\param[out] none
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\retval none
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*/
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void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state)
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{
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uint32_t port = 0U;
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/* enable or disable the external charge pump */
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usb_vbus_drive (state);
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/* turn on the host port power. */
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port = usb_port_read (pudev);
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if (!(port & HPCS_PP) && (1U == state)) {
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port |= HPCS_PP;
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}
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if ((port & HPCS_PP) && (0U == state)) {
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port &= ~HPCS_PP;
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}
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*pudev->regs.HPCS = port;
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usb_mdelay (200U);
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}
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/*!
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\brief reset host port
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\param[in] pudev: pointer to usb device
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\param[out] none
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\retval operation status
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*/
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uint32_t usb_port_reset (usb_core_driver *pudev)
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{
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__IO uint32_t port = usb_port_read (pudev);
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*pudev->regs.HPCS = port | HPCS_PRST;
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usb_mdelay(20U); /* see note */
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*pudev->regs.HPCS = port & ~HPCS_PRST;
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usb_mdelay(20U);
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return 1U;
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}
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/*!
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\brief initialize host pipe
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\param[in] pudev: pointer to usb device
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\param[in] pipe_num: host pipe number which is in (0..7)
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\param[out] none
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\retval operation status
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*/
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usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num)
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{
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usb_status status = USB_OK;
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__IO uint32_t pp_ctl = 0U;
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__IO uint32_t pp_inten = HCHINTEN_TFIE;
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usb_pipe *pp = &pudev->host.pipe[pipe_num];
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/* clear old interrupt conditions for this host channel */
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pudev->regs.pr[pipe_num]->HCHINTF = 0xFFFFFFFFU;
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if (USB_USE_DMA == pudev->bp.transfer_mode) {
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pp_inten |= HCHINTEN_DMAERIE;
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}
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if (pp->ep.dir) {
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pp_inten |= HCHINTEN_BBERIE;
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}
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/* enable channel interrupts required for this transfer */
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switch (pp->ep.type) {
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case USB_EPTYPE_CTRL:
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case USB_EPTYPE_BULK:
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pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE \
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| HCHINTEN_DTERIE | HCHINTEN_NAKIE;
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if (!pp->ep.dir) {
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pp_inten |= HCHINTEN_NYETIE;
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if (pp->ping) {
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pp_inten |= HCHINTEN_ACKIE;
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}
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}
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break;
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case USB_EPTYPE_INTR:
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pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \
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| HCHINTEN_NAKIE | HCHINTEN_REQOVRIE;
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break;
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case USB_EPTYPE_ISOC:
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pp_inten |= HCHINTEN_REQOVRIE | HCHINTEN_ACKIE;
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if (pp->ep.dir) {
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pp_inten |= HCHINTEN_USBERIE;
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}
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break;
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default:
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break;
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}
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pudev->regs.pr[pipe_num]->HCHINTEN = pp_inten;
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/* enable the top level host channel interrupt */
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pudev->regs.hr->HACHINTEN |= 1U << pipe_num;
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/* make sure host channel interrupts are enabled */
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pudev->regs.gr->GINTEN |= GINTEN_HCIE;
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/* program the host channel control register */
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pp_ctl |= PIPE_CTL_DAR(pp->dev_addr);
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pp_ctl |= PIPE_CTL_EPNUM(pp->ep.num);
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pp_ctl |= PIPE_CTL_EPDIR(pp->ep.dir);
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pp_ctl |= PIPE_CTL_EPTYPE(pp->ep.type);
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pp_ctl |= PIPE_CTL_LSD(pp->dev_speed == PORT_SPEED_LOW);
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pp_ctl |= pp->ep.mps;
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pp_ctl |= ((uint32_t)(pp->ep.type == USB_EPTYPE_INTR) << 29U) & HCHCTL_ODDFRM;
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pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl;
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return status;
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}
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/*!
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\brief prepare host channel for transferring packets
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\param[in] pudev: pointer to usb device
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\param[in] pipe_num: host pipe number which is in (0..7)
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\param[out] none
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\retval operation status
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*/
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usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num)
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{
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usb_status status = USB_OK;
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uint16_t dword_len = 0U;
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uint16_t packet_count = 0U;
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__IO uint32_t pp_ctl = 0U;
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usb_pipe *pp = &pudev->host.pipe[pipe_num];
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uint16_t max_packet_len = pp->ep.mps;
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/* compute the expected number of packets associated to the transfer */
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if (pp->xfer_len > 0U) {
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packet_count = (uint16_t)((pp->xfer_len + max_packet_len - 1U) / max_packet_len);
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if (packet_count > HC_MAX_PACKET_COUNT) {
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packet_count = HC_MAX_PACKET_COUNT;
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pp->xfer_len = (uint16_t)(packet_count * max_packet_len);
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}
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} else {
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packet_count = 1U;
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}
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if (pp->ep.dir) {
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pp->xfer_len = (uint16_t)(packet_count * max_packet_len);
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}
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/* initialize the host channel transfer information */
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pudev->regs.pr[pipe_num]->HCHLEN = pp->xfer_len | pp->DPID | PIPE_XFER_PCNT(packet_count);
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if (USB_USE_DMA == pudev->bp.transfer_mode) {
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pudev->regs.pr[pipe_num]->HCHDMAADDR = (unsigned int)pp->xfer_buf;
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}
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pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL;
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if (usb_frame_even(pudev)) {
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pp_ctl |= HCHCTL_ODDFRM;
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} else {
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pp_ctl &= ~HCHCTL_ODDFRM;
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}
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/* set host channel enabled */
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pp_ctl |= HCHCTL_CEN;
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pp_ctl &= ~HCHCTL_CDIS;
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pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl;
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if (USB_USE_FIFO == pudev->bp.transfer_mode) {
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if ((0U == pp->ep.dir) && (pp->xfer_len > 0U)) {
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switch (pp->ep.type) {
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/* non-periodic transfer */
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case USB_EPTYPE_CTRL:
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case USB_EPTYPE_BULK:
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dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U);
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/* check if there is enough space in fifo space */
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if (dword_len > (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
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/* need to process data in nptxfempty interrupt */
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pudev->regs.gr->GINTEN |= GINTEN_NPTXFEIE;
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}
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break;
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/* periodic transfer */
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case USB_EPTYPE_INTR:
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case USB_EPTYPE_ISOC:
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dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U);
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/* check if there is enough space in fifo space */
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if (dword_len > (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) {
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/* need to process data in ptxfempty interrupt */
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pudev->regs.gr->GINTEN |= GINTEN_PTXFEIE;
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}
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break;
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default:
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break;
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}
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/* write packet into the tx fifo. */
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usb_txfifo_write (&pudev->regs, pp->xfer_buf, pipe_num, (uint16_t)pp->xfer_len);
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}
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}
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return status;
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}
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/*!
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\brief halt pipe
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\param[in] pudev: pointer to usb device
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\param[in] pipe_num: host pipe number which is in (0..7)
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\param[out] none
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\retval operation status
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*/
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usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num)
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{
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__IO uint32_t pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL;
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uint8_t ep_type = (uint8_t)((pp_ctl & HCHCTL_EPTYPE) >> 18U);
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pp_ctl |= HCHCTL_CEN | HCHCTL_CDIS;
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switch (ep_type) {
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case USB_EPTYPE_CTRL:
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case USB_EPTYPE_BULK:
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if (0U == (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
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pp_ctl &= ~HCHCTL_CEN;
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}
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break;
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case USB_EPTYPE_INTR:
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case USB_EPTYPE_ISOC:
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if (0U == (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) {
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pp_ctl &= ~HCHCTL_CEN;
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}
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break;
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default:
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break;
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}
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pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl;
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return USB_OK;
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}
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/*!
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\brief configure host pipe to do ping operation
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\param[in] pudev: pointer to usb device
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\param[in] pipe_num: host pipe number which is in (0..7)
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\param[out] none
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\retval operation status
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*/
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usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num)
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{
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uint32_t pp_ctl = 0U;
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pudev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U));
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pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL;
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pp_ctl |= HCHCTL_CEN;
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pp_ctl &= ~HCHCTL_CDIS;
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pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl;
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return USB_OK;
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}
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/*!
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\brief stop the USB host and clean up FIFO
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\param[in] pudev: pointer to usb device
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\param[out] none
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\retval none
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*/
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void usb_host_stop (usb_core_driver *pudev)
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{
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uint32_t i;
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__IO uint32_t pp_ctl = 0U;
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pudev->regs.hr->HACHINTEN = 0x0U;
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pudev->regs.hr->HACHINT = 0xFFFFFFFFU;
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/* flush out any leftover queued requests. */
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for (i = 0U; i < pudev->bp.num_pipe; i++) {
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pp_ctl = pudev->regs.pr[i]->HCHCTL;
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pp_ctl &= ~(HCHCTL_CEN | HCHCTL_EPDIR);
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pp_ctl |= HCHCTL_CDIS;
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pudev->regs.pr[i]->HCHCTL = pp_ctl;
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}
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/* flush the FIFO */
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usb_rxfifo_flush (&pudev->regs);
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usb_txfifo_flush (&pudev->regs, 0x10U);
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}
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