/*!
|
\file drv_usb_dev.c
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\brief USB device mode low level driver
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\version 2020-08-01, V3.0.0, firmware for GD32F30x
|
*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "drv_usb_hw.h"
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#include "drv_usb_core.h"
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#include "drv_usb_dev.h"
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/* endpoint 0 max packet length */
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static const uint8_t EP0_MAXLEN[4] = {
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[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64,
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[DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64,
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[DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64,
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[DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8
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};
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#ifdef USB_FS_CORE
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/* USB endpoint Tx FIFO size */
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static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] =
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{
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(uint16_t)TX0_FIFO_FS_SIZE,
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(uint16_t)TX1_FIFO_FS_SIZE,
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(uint16_t)TX2_FIFO_FS_SIZE,
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(uint16_t)TX3_FIFO_FS_SIZE
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};
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#endif /* USBFS_CORE */
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/*!
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\brief initialize USB core registers for device mode
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\param[in] udev: pointer to USB device
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\param[out] none
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\retval operation status
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*/
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usb_status usb_devcore_init (usb_core_driver *udev)
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{
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uint8_t i;
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/* restart the PHY clock (maybe don't need to...) */
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*udev->regs.PWRCLKCTL = 0U;
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/* config periodic frame interval to default value */
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udev->regs.dr->DCFG &= ~DCFG_EOPFT;
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udev->regs.dr->DCFG |= FRAME_INTERVAL_80;
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udev->regs.dr->DCFG &= ~DCFG_DS;
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#ifdef USB_FS_CORE
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if (udev->bp.core_enum == (uint8_t)USB_CORE_ENUM_FS) {
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/* set full-speed PHY */
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udev->regs.dr->DCFG |= USB_SPEED_INP_FULL;
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/* set Rx FIFO size */
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usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE);
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/* set endpoint 0 to 3's Tx FIFO length and RAM address */
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for (i = 0U; i < USBFS_MAX_EP_COUNT; i++) {
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usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]);
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}
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}
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#endif /* USB_FS_CORE */
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/* make sure all FIFOs are flushed */
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/* flush all Tx FIFOs */
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(void)usb_txfifo_flush (&udev->regs, 0x10U);
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/* flush entire Rx FIFO */
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(void)usb_rxfifo_flush (&udev->regs);
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/* clear all pending device interrupts */
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udev->regs.dr->DIEPINTEN = 0U;
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udev->regs.dr->DOEPINTEN = 0U;
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udev->regs.dr->DAEPINT = 0xFFFFFFFFU;
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udev->regs.dr->DAEPINTEN = 0U;
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/* configure all IN/OUT endpoints */
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for (i = 0U; i < udev->bp.num_ep; i++) {
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if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) {
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udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK;
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} else {
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udev->regs.er_in[i]->DIEPCTL = 0U;
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}
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/* set IN endpoint transfer length to 0 */
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udev->regs.er_in[i]->DIEPLEN = 0U;
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/* clear all pending IN endpoint interrupts */
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udev->regs.er_in[i]->DIEPINTF = 0xFFU;
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if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) {
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udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK;
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} else {
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udev->regs.er_out[i]->DOEPCTL = 0U;
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}
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/* set OUT endpoint transfer length to 0 */
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udev->regs.er_out[i]->DOEPLEN = 0U;
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/* clear all pending OUT endpoint interrupts */
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udev->regs.er_out[i]->DOEPINTF = 0xFFU;
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}
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udev->regs.dr->DIEPINTEN |= DIEPINTEN_EPTXFUDEN;
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(void)usb_devint_enable (udev);
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return USB_OK;
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}
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/*!
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\brief enable the USB device mode interrupts
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\param[in] udev: pointer to USB device
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\param[out] none
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\retval operation status
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*/
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usb_status usb_devint_enable (usb_core_driver *udev)
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{
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/* clear any pending USB OTG interrupts */
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udev->regs.gr->GOTGINTF = 0xFFFFFFFFU;
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/* clear any pending interrupts */
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udev->regs.gr->GINTF = 0xBFFFFFFFU;
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/* enable the USB wakeup and suspend interrupts */
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udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
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/* enable device_mode-related interrupts */
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if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) {
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udev->regs.gr->GINTEN |= GINTEN_RXFNEIE;
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}
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udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\
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GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE | GINTEN_ISOINCIE;
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#ifdef VBUS_SENSING_ENABLED
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udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE;
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#endif /* VBUS_SENSING_ENABLED */
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return USB_OK;
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}
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/*!
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\brief active the USB endpoint0 transaction
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\param[in] udev: pointer to USB device
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\param[in] transc: the USB endpoint0 transaction
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\param[out] none
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\retval operation status
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*/
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usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc)
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{
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__IO uint32_t *reg_addr = NULL;
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/* get the endpoint number */
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uint8_t ep_num = transc->ep_addr.num;
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if (ep_num) {
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/* not endpoint 0 */
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return USB_FAIL;
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}
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if (transc->ep_addr.dir) {
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reg_addr = &udev->regs.er_in[0]->DIEPCTL;
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} else {
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reg_addr = &udev->regs.er_out[0]->DOEPCTL;
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}
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/* endpoint 0 is activated after USB clock is enabled */
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*reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM);
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/* set endpoint 0 maximum packet length */
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*reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES];
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/* activate endpoint */
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*reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT;
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return USB_OK;
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}
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/*!
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\brief active the USB transaction
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\param[in] udev: pointer to USB device
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\param[in] transc: the USB transaction
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\param[out] none
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\retval status
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*/
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usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
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{
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__IO uint32_t *reg_addr = NULL;
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__IO uint32_t epinten = 0U;
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/* get the endpoint number */
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uint8_t ep_num = transc->ep_addr.num;
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/* enable endpoint interrupt number */
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if (transc->ep_addr.dir) {
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reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL;
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epinten = 1U << ep_num;
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} else {
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reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL;
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epinten = 1U << (16U + ep_num);
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}
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/* if the endpoint is not active, need change the endpoint control register */
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if (!(*reg_addr & DEPCTL_EPACT)) {
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*reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM);
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/* set endpoint maximum packet length */
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if (0U == ep_num) {
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*reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES];
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} else {
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*reg_addr |= transc->max_len;
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}
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/* activate endpoint */
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*reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT;
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}
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/* enable the interrupts for this endpoint */
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udev->regs.dr->DAEPINTEN |= epinten;
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return USB_OK;
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}
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/*!
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\brief deactivate the USB transaction
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\param[in] udev: pointer to USB device
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\param[in] transc: the USB transaction
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\param[out] none
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\retval status
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*/
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usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc)
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{
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uint32_t epinten = 0U;
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uint8_t ep_num = transc->ep_addr.num;
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/* disable endpoint interrupt number */
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if (transc->ep_addr.dir) {
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epinten = 1U << ep_num;
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udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT;
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} else {
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epinten = 1U << (ep_num + 16U);
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udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT;
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}
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/* disable the interrupts for this endpoint */
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udev->regs.dr->DAEPINTEN &= ~epinten;
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return USB_OK;
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}
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/*!
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\brief configure USB transaction to start IN transfer
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\param[in] udev: pointer to USB device
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\param[in] transc: the USB IN transaction
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\param[out] none
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\retval operation status
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*/
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usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
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{
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usb_status status = USB_OK;
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uint8_t ep_num = transc->ep_addr.num;
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__IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL;
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__IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN;
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eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT);
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/* zero length packet or endpoint 0 */
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if (0U == transc->xfer_len) {
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/* set transfer packet count to 1 */
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eplen |= 1U << 19U;
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} else {
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/* set transfer packet count */
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if (0U == ep_num) {
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transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len);
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eplen |= 1U << 19U;
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} else {
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eplen |= (((transc->xfer_len - 1U) + transc->max_len) / transc->max_len) << 19U;
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}
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/* set endpoint transfer length */
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eplen |= transc->xfer_len;
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if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) {
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eplen |= DIEPLEN_MCNT & (1U << 29U);
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}
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}
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udev->regs.er_in[ep_num]->DIEPLEN = eplen;
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if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) {
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if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) {
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epctl |= DEPCTL_SEVNFRM;
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} else {
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epctl |= DEPCTL_SODDFRM;
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}
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}
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if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
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udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr;
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}
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/* enable the endpoint and clear the NAK */
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epctl |= DEPCTL_CNAK | DEPCTL_EPEN;
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udev->regs.er_in[ep_num]->DIEPCTL = epctl;
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if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) {
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udev->regs.er_in[ep_num]->DIEPCTL = epctl;
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if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) {
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/* enable the Tx FIFO empty interrupt for this endpoint */
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if (transc->xfer_len > 0U) {
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udev->regs.dr->DIEPFEINTEN |= 1U << ep_num;
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}
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} else {
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(void)usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, (uint16_t)transc->xfer_len);
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}
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}
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return status;
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}
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/*!
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\brief configure usb transaction to start OUT transfer
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\param[in] udev: pointer to usb device
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\param[in] transc: the usb OUT transaction
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\param[out] none
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\retval status
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*/
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usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc)
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{
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usb_status status = USB_OK;
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uint8_t ep_num = transc->ep_addr.num;
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uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL;
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uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN;
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eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT);
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/* zero length packet or endpoint 0 */
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if ((0U == transc->xfer_len) || (0U == ep_num)) {
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/* set the transfer length to max packet size */
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eplen |= transc->max_len;
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/* set the transfer packet count to 1 */
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eplen |= 1U << 19U;
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} else {
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/* configure the transfer size and packet count as follows:
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* pktcnt = N
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* xfersize = N * maxpacket
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*/
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uint32_t packet_count = (transc->xfer_len + transc->max_len - 1U) / transc->max_len;
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eplen |= packet_count << 19U;
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eplen |= packet_count * transc->max_len;
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}
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udev->regs.er_out[ep_num]->DOEPLEN = eplen;
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if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
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udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr;
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}
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if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) {
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if (transc->frame_num) {
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epctl |= DEPCTL_SD1PID;
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} else {
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epctl |= DEPCTL_SD0PID;
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}
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}
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/* enable the endpoint and clear the NAK */
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epctl |= DEPCTL_EPEN | DEPCTL_CNAK;
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udev->regs.er_out[ep_num]->DOEPCTL = epctl;
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return status;
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}
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/*!
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\brief set the USB transaction STALL status
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\param[in] udev: pointer to USB device
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\param[in] transc: the USB transaction
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\param[out] none
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\retval status
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*/
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usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc)
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{
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__IO uint32_t *reg_addr = NULL;
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uint8_t ep_num = transc->ep_addr.num;
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if (transc->ep_addr.dir) {
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reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL);
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/* set the endpoint disable bit */
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if (*reg_addr & DEPCTL_EPEN) {
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*reg_addr |= DEPCTL_EPD;
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}
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} else {
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/* set the endpoint stall bit */
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reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL);
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}
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/* set the endpoint stall bit */
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*reg_addr |= DEPCTL_STALL;
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return USB_OK;
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}
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/*!
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\brief clear the USB transaction STALL status
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\param[in] udev: pointer to USB device
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\param[in] transc: the USB transaction
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\param[out] none
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\retval operation status
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*/
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usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc)
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{
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__IO uint32_t *reg_addr = NULL;
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uint8_t ep_num = transc->ep_addr.num;
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if (transc->ep_addr.dir) {
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reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL);
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} else {
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reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL);
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}
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/* clear the endpoint stall bits */
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*reg_addr &= ~DEPCTL_STALL;
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/* reset data PID of the periodic endpoints */
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if ((transc->ep_type == (uint8_t)USB_EPTYPE_INTR) || (transc->ep_type == (uint8_t)USB_EPTYPE_BULK)) {
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*reg_addr |= DEPCTL_SD0PID;
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}
|
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return USB_OK;
|
}
|
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/*!
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\brief read device IN endpoint interrupt flag register
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\param[in] udev: pointer to USB device
|
\param[in] ep_num: endpoint number
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\param[out] none
|
\retval interrupt value
|
*/
|
uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num)
|
{
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uint32_t value = 0U, fifoemptymask, commonintmask;
|
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commonintmask = udev->regs.dr->DIEPINTEN;
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fifoemptymask = udev->regs.dr->DIEPFEINTEN;
|
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/* check FIFO empty interrupt enable bit */
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commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7;
|
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value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask;
|
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return value;
|
}
|
|
/*!
|
\brief configures OUT endpoint 0 to receive SETUP packets
|
\param[in] udev: pointer to USB device
|
\param[out] none
|
\retval none
|
*/
|
void usb_ctlep_startout (usb_core_driver *udev)
|
{
|
/* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */
|
udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U);
|
|
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
|
udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req;
|
|
/* endpoint enable */
|
udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN;
|
}
|
}
|
|
/*!
|
\brief active remote wakeup signaling
|
\param[in] udev: pointer to USB device
|
\param[out] none
|
\retval none
|
*/
|
void usb_rwkup_active (usb_core_driver *udev)
|
{
|
if (udev->dev.pm.dev_remote_wakeup) {
|
if (udev->regs.dr->DSTAT & DSTAT_SPST) {
|
if (udev->bp.low_power) {
|
/* ungate USB core clock */
|
*udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK);
|
}
|
|
/* active remote wakeup signaling */
|
udev->regs.dr->DCTL |= DCTL_RWKUP;
|
|
usb_mdelay(5U);
|
|
udev->regs.dr->DCTL &= ~DCTL_RWKUP;
|
}
|
}
|
}
|
|
/*!
|
\brief active USB core clock
|
\param[in] udev: pointer to USB device
|
\param[out] none
|
\retval none
|
*/
|
void usb_clock_active (usb_core_driver *udev)
|
{
|
if (udev->bp.low_power) {
|
if (udev->regs.dr->DSTAT & DSTAT_SPST) {
|
/* un-gate USB Core clock */
|
*udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK);
|
}
|
}
|
}
|
|
/*!
|
\brief USB device suspend
|
\param[in] udev: pointer to USB device
|
\param[out] none
|
\retval none
|
*/
|
void usb_dev_suspend (usb_core_driver *udev)
|
{
|
__IO uint32_t devstat = udev->regs.dr->DSTAT;
|
|
if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) {
|
/* switch-off the USB clocks */
|
*udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK;
|
|
/* enter DEEP_SLEEP mode with LDO in low power mode */
|
pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
|
}
|
}
|
|
/*!
|
\brief stop the device and clean up FIFOs
|
\param[in] udev: pointer to USB device
|
\param[out] none
|
\retval none
|
*/
|
void usb_dev_stop (usb_core_driver *udev)
|
{
|
uint32_t i;
|
|
udev->dev.cur_status = 1U;
|
|
/* clear all interrupt flag and enable bits */
|
for (i = 0U; i < udev->bp.num_ep; i++) {
|
udev->regs.er_in[i]->DIEPINTF = 0xFFU;
|
udev->regs.er_out[i]->DOEPINTF = 0xFFU;
|
}
|
|
udev->regs.dr->DIEPINTEN = 0U;
|
udev->regs.dr->DOEPINTEN = 0U;
|
udev->regs.dr->DAEPINTEN = 0U;
|
udev->regs.dr->DAEPINT = 0xFFFFFFFFU;
|
|
/* flush the FIFO */
|
(void)usb_rxfifo_flush (&udev->regs);
|
(void)usb_txfifo_flush (&udev->regs, 0x10U);
|
}
|
