/*!
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\file drv_usb_core.c
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\brief USB core driver which can operate in host and device mode
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\version 2020-08-01, V3.0.0, firmware for GD32F30x
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "drv_usb_core.h"
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#include "drv_usb_hw.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* local function prototypes ('static') */
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static void usb_core_reset (usb_core_regs *usb_regs);
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#ifdef __cplusplus
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}
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#endif
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/*!
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\brief configure USB core basic
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\param[in] usb_basic: pointer to usb capabilities
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\param[in] usb_regs: USB core registers
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\param[in] usb_core: USB core
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\param[out] none
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\retval operation status
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*/
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usb_status usb_basic_init (usb_core_basic *usb_basic,
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usb_core_regs *usb_regs,
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usb_core_enum usb_core)
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{
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/* configure USB default transfer mode as FIFO mode */
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usb_basic->transfer_mode = (uint8_t)USB_USE_FIFO;
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/* USB default speed is full-speed */
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usb_basic->core_speed = (uint8_t)USB_SPEED_FULL;
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usb_basic->core_enum = (uint8_t)usb_core;
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switch (usb_core) {
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case USB_CORE_ENUM_FS:
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usb_basic->base_reg = (uint32_t)USBFS_REG_BASE;
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/* set the host channel numbers */
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usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT;
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/* set the device endpoint numbers */
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usb_basic->num_ep = USBFS_MAX_EP_COUNT;
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/* USBFS core use embedded physical layer */
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usb_basic->phy_itf = USB_EMBEDDED_PHY;
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break;
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default:
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return USB_FAIL;
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}
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usb_basic->sof_enable = USB_SOF_OUTPUT;
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usb_basic->low_power = USB_LOW_POWER;
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/* assign main registers address */
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/*
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*usb_regs = (usb_core_regs) {
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.gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE),
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.hr = (usb_hr*) (usb_basic->base_reg + USB_REG_OFFSET_HOST),
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.dr = (usb_dr*) (usb_basic->base_reg + USB_REG_OFFSET_DEV),
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.HPCS = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PORT),
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.PWRCLKCTL = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PWRCLKCTL)
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};
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*/
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{
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usb_regs->gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE);
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usb_regs->hr = (usb_hr*) (usb_basic->base_reg + USB_REG_OFFSET_HOST);
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usb_regs->dr = (usb_dr*) (usb_basic->base_reg + USB_REG_OFFSET_DEV);
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usb_regs->HPCS = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PORT);
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usb_regs->PWRCLKCTL = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PWRCLKCTL);
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}
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/* assign device endpoint registers address */
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for (uint8_t i = 0U; i < usb_basic->num_ep; i++) {
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usb_regs->er_in[i] = (usb_erin *) \
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(usb_basic->base_reg + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP));
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usb_regs->er_out[i] = (usb_erout *)\
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(usb_basic->base_reg + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP));
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}
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/* assign host pipe registers address */
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for (uint8_t i = 0U; i < usb_basic->num_pipe; i++) {
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usb_regs->pr[i] = (usb_pr *) \
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(usb_basic->base_reg + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH));
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usb_regs->DFIFO[i] = (uint32_t *) \
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(usb_basic->base_reg + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE));
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}
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return USB_OK;
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}
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/*!
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\brief initializes the USB controller registers and
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prepares the core device mode or host mode operation
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\param[in] usb_basic: pointer to USB capabilities
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\param[in] usb_regs: pointer to USB core registers
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\param[out] none
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\retval operation status
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*/
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usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
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{
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if (USB_ULPI_PHY == usb_basic.phy_itf) {
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usb_regs->gr->GCCFG &= ~GCCFG_PWRON;
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if (usb_basic.sof_enable) {
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usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
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}
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/* init the ULPI interface */
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usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI);
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#ifdef USBHS_EXTERNAL_VBUS_ENABLED
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/* use external VBUS driver */
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usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD;
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#else
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/* use internal VBUS driver */
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usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD;
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#endif /* USBHS_EXTERNAL_VBUS_ENABLED */
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/* soft reset the core */
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usb_core_reset (usb_regs);
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} else {
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usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY;
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/* soft reset the core */
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usb_core_reset (usb_regs);
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/* active the transceiver and enable VBUS sensing */
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usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
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#ifndef VBUS_SENSING_ENABLED
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usb_regs->gr->GCCFG |= GCCFG_VBUSIG;
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#endif /* VBUS_SENSING_ENABLED */
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/* enable SOF output */
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if (usb_basic.sof_enable) {
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usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
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}
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usb_mdelay(20U);
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}
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if ((uint8_t)USB_USE_DMA == usb_basic.transfer_mode) {
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usb_regs->gr->GAHBCS &= ~GAHBCS_BURST;
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usb_regs->gr->GAHBCS |= DMA_INCR8 | GAHBCS_DMAEN;
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}
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#ifdef USE_OTG_MODE
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/* enable USB OTG features */
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usb_regs->gr->GUSBCS |= GUSBCS_HNPCEN | GUSBCS_SRPCEN;
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/* enable the USB wakeup and suspend interrupts */
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usb_regs->gr->GINTF = 0xBFFFFFFFU;
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usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \
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GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE;
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#endif /* USE_OTG_MODE */
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return USB_OK;
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}
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/*!
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\brief write a packet into the Tx FIFO associated with the endpoint
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\param[in] usb_regs: pointer to USB core registers
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\param[in] src_buf: pointer to source buffer
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\param[in] fifo_num: FIFO number which is in (0..3)
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\param[in] byte_count: packet byte count
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\param[out] none
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\retval operation status
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*/
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usb_status usb_txfifo_write (usb_core_regs *usb_regs,
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uint8_t *src_buf,
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uint8_t fifo_num,
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uint16_t byte_count)
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{
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uint32_t word_count = (byte_count + 3U) / 4U;
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__IO uint32_t *fifo = usb_regs->DFIFO[fifo_num];
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while (word_count-- > 0U) {
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*fifo = *((__packed uint32_t *)src_buf);
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src_buf += 4U;
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}
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return USB_OK;
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}
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/*!
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\brief read a packet from the Rx FIFO associated with the endpoint
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\param[in] usb_regs: pointer to USB core registers
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\param[in] dest_buf: pointer to destination buffer
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\param[in] byte_count: packet byte count
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\param[out] none
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\retval void type pointer
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*/
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void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count)
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{
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uint32_t word_count = (byte_count + 3U) / 4U;
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__IO uint32_t *fifo = usb_regs->DFIFO[0];
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while (word_count-- > 0U) {
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*(__packed uint32_t *)dest_buf = *fifo;
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dest_buf += 4U;
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}
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return ((void *)dest_buf);
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}
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/*!
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\brief flush a Tx FIFO or all Tx FIFOs
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\param[in] usb_regs: pointer to USB core registers
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\param[in] fifo_num: FIFO number which is in (0..3)
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\param[out] none
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\retval operation status
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*/
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usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num)
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{
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usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
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/* wait for Tx FIFO flush bit is set */
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while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) {
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/* no operation */
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}
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/* wait for 3 PHY clocks*/
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usb_udelay(3U);
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return USB_OK;
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}
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/*!
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\brief flush the entire Rx FIFO
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\param[in] usb_regs: pointer to usb core registers
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\param[out] none
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\retval operation status
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*/
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usb_status usb_rxfifo_flush (usb_core_regs *usb_regs)
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{
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usb_regs->gr->GRSTCTL = GRSTCTL_RXFF;
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/* wait for Rx FIFO flush bit is set */
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while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) {
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/* no operation */
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}
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/* wait for 3 PHY clocks */
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usb_udelay(3U);
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return USB_OK;
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}
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/*!
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\brief set endpoint or channel TX FIFO size
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\param[in] usb_regs: pointer to USB core registers
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\param[in] fifo: TX FIFO number
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\param[in] size: assigned TX FIFO size
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\param[out] none
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\retval none
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*/
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void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size)
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{
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uint32_t tx_offset;
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tx_offset = usb_regs->gr->GRFLEN;
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if (fifo == 0U) {
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usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset;
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} else {
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tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16;
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for (uint8_t i = 0U; i < (fifo - 1U); i++) {
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tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16);
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}
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/* Multiply Tx_Size by 2 to get higher performance */
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usb_regs->gr->DIEPTFLEN[fifo - 1U] = ((uint32_t)size << 16) | tx_offset;
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}
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}
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/*!
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\brief set USB current mode
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\param[in] usb_regs: pointer to USB core registers
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\param[out] none
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\retval none
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*/
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void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode)
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{
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usb_regs->gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM);
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if (DEVICE_MODE == mode) {
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usb_regs->gr->GUSBCS |= GUSBCS_FDM;
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} else if (HOST_MODE == mode) {
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usb_regs->gr->GUSBCS |= GUSBCS_FHM;
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} else {
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/* OTG mode and other mode can not be here! */
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}
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}
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*!
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\brief configure USB core to soft reset
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\param[in] usb_regs: pointer to USB core registers
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\param[out] none
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\retval none
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*/
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static void usb_core_reset (usb_core_regs *usb_regs)
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{
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/* enable core soft reset */
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usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST;
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/* wait for the core to be soft reset */
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while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) {
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/* no operation */
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}
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/* wait for additional 3 PHY clocks */
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usb_udelay(3U);
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}
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#ifdef __cplusplus
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}
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#endif
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