/*!
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\file usbd_lld_regs.h
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\brief USB device low level registers
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\version 2020-08-01, V3.0.0, firmware for GD32F30x
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef __USBD_LLD_REGS_H
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#define __USBD_LLD_REGS_H
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#include "usbd_conf.h"
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/* USB device registers base address */
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#define USBD USBD_BASE
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#define USBD_RAM USBD_RAM_BASE
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/* registers definitions */
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/* common registers */
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#define USBD_CTL (REG32(USBD + 0x40U)) /*!< control register */
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#define USBD_INTF (REG32(USBD + 0x44U)) /*!< interrupt flag register */
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#define USBD_STAT (REG32(USBD + 0x48U)) /*!< status register */
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#define USBD_DADDR (REG32(USBD + 0x4CU)) /*!< device address register */
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#define USBD_BADDR (REG32(USBD + 0x50U)) /*!< buffer address register */
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#define USBD_LPMCS (REG32(USBD + 0x54U)) /*!< USBD LPM control and status register */
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/* endpoint control and status register */
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#define USBD_EPxCS(ep_num) (REG32(USBD + (ep_num) * 4U)) /*!< endpoint x control and status register address */
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/* bits definitions */
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/* USBD_CTL */
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#define CTL_STIE BIT(15) /*!< successful transfer interrupt enable mask */
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#define CTL_PMOUIE BIT(14) /*!< packet memory overrun/underrun interrupt enable mask */
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#define CTL_ERRIE BIT(13) /*!< error interrupt enable mask */
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#define CTL_WKUPIE BIT(12) /*!< wakeup interrupt enable mask */
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#define CTL_SPSIE BIT(11) /*!< suspend state interrupt enable mask */
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#define CTL_RSTIE BIT(10) /*!< reset interrupt enable mask */
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#define CTL_SOFIE BIT(9) /*!< start of frame interrupt enable mask */
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#define CTL_ESOFIE BIT(8) /*!< expected start of frame interrupt enable mask */
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#define CTL_L1REQIE BIT(7) /*!< LPM L1 state request interrupt enable */
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#define CTL_L1RSREQ BIT(5) /*!< LPM L1 resume request */
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#define CTL_RSREQ BIT(4) /*!< resume request */
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#define CTL_SETSPS BIT(3) /*!< set suspend state */
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#define CTL_LOWM BIT(2) /*!< low-power mode at suspend state */
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#define CTL_CLOSE BIT(1) /*!< goes to close state */
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#define CTL_SETRST BIT(0) /*!< set USB reset */
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#ifdef LPM_ENABLED
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#define USBD_INTEN BITS(7, 15) /*!< USBD interrupt enable bits */
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#else
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#define USBD_INTEN BITS(8, 15) /*!< USBD interrupt enable bits */
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#endif
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/* USBD_INTF */
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#define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */
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#define INTF_PMOUIF BIT(14) /*!< packet memory overrun/underrun interrupt flag (clear-only bit) */
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#define INTF_ERRIF BIT(13) /*!< error interrupt flag (clear-only bit) */
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#define INTF_WKUPIF BIT(12) /*!< wakeup interrupt flag (clear-only bit) */
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#define INTF_SPSIF BIT(11) /*!< suspend state interrupt flag (clear-only bit) */
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#define INTF_RSTIF BIT(10) /*!< reset interrupt flag (clear-only bit) */
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#define INTF_SOFIF BIT(9) /*!< start of frame interrupt flag (clear-only bit) */
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#define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */
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#define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */
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#define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */
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#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */
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/* USBD_STAT */
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#define STAT_RXDP BIT(15) /*!< data plus line status */
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#define STAT_RXDM BIT(14) /*!< data minus line status */
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#define STAT_LOCK BIT(13) /*!< locked the USB */
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#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */
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#define STAT_FCNT BITS(0, 10) /*!< frame number count */
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/* USBD_DADDR */
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#define DADDR_USBEN BIT(7) /*!< USB module enable */
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#define DADDR_USBADDR BITS(0, 6) /*!< USB device address */
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/* USBD_EPxCS */
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#define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */
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#define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */
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#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */
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#define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */
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#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */
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#define EPxCS_KCTL BIT(8) /*!< endpoint kind control */
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#define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */
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#define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */
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#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */
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#define EPxCS_AR BITS(0, 3) /*!< endpoint address */
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/* USBD_LPMCS */
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#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */
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#define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */
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#define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */
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#define LPMCS_LPMEN BIT(0) /*!< LPM support enable */
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/* constants definitions */
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/* endpoint control and status register mask (no toggle fields) */
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#define EPCS_MASK (EPxCS_RX_ST | EPxCS_SETUP | \
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EPxCS_CTL | EPxCS_KCTL | EPxCS_TX_ST | EPxCS_AR)
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/* EPxCS_CTL[1:0] endpoint type control */
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#define ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U))
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#define EP_BULK ENDP_TYPE(0U) /* bulk transfers */
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#define EP_CONTROL ENDP_TYPE(1U) /* control transfers */
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#define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */
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#define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */
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#define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK)
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/* endpoint kind control mask */
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#define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK)
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/* EPxCS_TX_STA[1:0] status for Tx transfer */
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#define ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U))
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#define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */
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#define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */
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#define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */
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#define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */
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#define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK)
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/* EPxCS_RX_STA[1:0] status for Rx transfer */
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#define ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U))
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#define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */
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#define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */
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#define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */
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#define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */
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#define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK)
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/* endpoint receive/transmission counter register bit definitions */
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#define EPRCNT_BLKSIZ BIT(15) /* reception data block size */
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#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */
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#define EPRCNT_CNT BITS(0, 9) /* reception data count */
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#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */
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/* interrupt flag clear bits */
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#define CLR(x) (USBD_INTF = ~INTF_##x)
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/* endpoint receive/transmission counter register bit offset */
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#define BLKSIZE_OFFSET (0x01U)
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#define BLKNUM_OFFSET (0x05U)
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#define RXCNT_OFFSET (0x0AU)
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#define TXCNT_OFFSET (0x0AU)
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#define BLKSIZE32_MASK (0x1fU)
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#define BLKSIZE2_MASK (0x01U)
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#define BLKSIZE32_OFFSETMASK (0x05U)
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#define BLKSIZE2_OFFSETMASK (0x01U)
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/* USBD operation macros */
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/* Tx or Rx transfer status setting (bits EPTX_STA[1:0]) */
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#define USBD_EP_TX_STAT_SET(ep, stat) do {\
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USBD_EPxCS(ep) = (USBD_EPxCS(ep) & (uint16_t)EPTX_DTGMASK) ^ (stat); \
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} while(0)
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#define USBD_EP_RX_STAT_SET(ep, stat) do {\
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USBD_EPxCS(ep) = (USBD_EPxCS(ep) & (uint16_t)EPRX_DTGMASK) ^ (stat); \
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} while(0)
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/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */
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#define USBD_EP_TX_ST_CLEAR(ep) do {\
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USBD_EPxCS(ep) &= ~EPxCS_TX_ST & (uint16_t)EPCS_MASK; \
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} while(0)
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#define USBD_EP_RX_ST_CLEAR(ep) do {\
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USBD_EPxCS(ep) &= ~EPxCS_RX_ST & (uint16_t)EPCS_MASK; \
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} while(0)
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/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */
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#define USBD_TX_DTG_TOGGLE(ep) do {\
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USBD_EPxCS(ep) = EPxCS_TX_DTG | (USBD_EPxCS(ep) & EPCS_MASK); \
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} while(0)
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#define USBD_RX_DTG_TOGGLE(ep) do {\
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USBD_EPxCS(ep) = EPxCS_RX_DTG | (USBD_EPxCS(ep) & EPCS_MASK); \
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} while(0)
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/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */
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#define USBD_TX_DTG_CLEAR(ep) do {\
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if ((USBD_EPxCS(ep_num) & EPxCS_TX_DTG) != 0U) {\
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USBD_TX_DTG_TOGGLE(ep);\
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} \
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} while(0)
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#define USBD_RX_DTG_CLEAR(ep) do {\
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if ((USBD_EPxCS(ep_num) & EPxCS_RX_DTG) != 0U) {\
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USBD_RX_DTG_TOGGLE(ep);\
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} \
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} while(0)
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#define USBD_EP_DBL_BUF_SET(ep) (USBD_EPxCS(ep) = (USBD_EPxCS(ep) | EPxCS_KCTL) & EPCS_MASK)
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#endif /* __USBD_LLD_REGS_H */
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