/*!
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\file gd32f30x_dbg.c
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\brief DBG driver
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\version 2017-02-10, V1.0.0, firmware for GD32F30x
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\version 2018-10-10, V1.1.0, firmware for GD32F30x
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\version 2018-12-25, V2.0.0, firmware for GD32F30x
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\version 2020-09-30, V2.1.0, firmware for GD32F30x
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32f30x_dbg.h"
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#define DBG_RESET_VAL 0x00000000U
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/*!
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\brief deinitialize the DBG
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dbg_deinit(void)
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{
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DBG_CTL0 = DBG_RESET_VAL;
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}
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/*!
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\brief read DBG_ID code register
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\param[in] none
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\param[out] none
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\retval DBG_ID code
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*/
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uint32_t dbg_id_get(void)
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{
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return DBG_ID;
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}
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/*!
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\brief enable low power behavior when the mcu is in debug mode
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\param[in] dbg_low_power:
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this parameter can be any combination of the following values:
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\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
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\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
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\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
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\param[out] none
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\retval none
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*/
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void dbg_low_power_enable(uint32_t dbg_low_power)
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{
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DBG_CTL0 |= dbg_low_power;
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}
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/*!
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\brief disable low power behavior when the mcu is in debug mode
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\param[in] dbg_low_power:
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this parameter can be any combination of the following values:
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\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
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\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
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\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
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\param[out] none
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\retval none
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*/
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void dbg_low_power_disable(uint32_t dbg_low_power)
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{
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DBG_CTL0 &= ~dbg_low_power;
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}
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/*!
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\brief enable peripheral behavior when the mcu is in debug mode
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\param[in] dbg_periph: refer to dbg_periph_enum
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only one parameter can be selected which is shown as below:
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\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
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\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
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\arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted
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\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
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\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
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\param[out] none
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\retval none
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*/
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void dbg_periph_enable(dbg_periph_enum dbg_periph)
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{
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DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
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}
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/*!
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\brief disable peripheral behavior when the mcu is in debug mode
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\param[in] dbg_periph: refer to dbg_periph_enum
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only one parameter can be selected which is shown as below:
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\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
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\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
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\arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted
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\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
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\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
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\param[out] none
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\retval none
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*/
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void dbg_periph_disable(dbg_periph_enum dbg_periph)
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{
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DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
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}
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/*!
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\brief enable trace pin assignment
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dbg_trace_pin_enable(void)
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{
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DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
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}
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/*!
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\brief disable trace pin assignment
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dbg_trace_pin_disable(void)
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{
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DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
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}
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/*!
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\brief trace pin mode selection
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\param[in] trace_mode:
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\arg TRACE_MODE_ASYNC: trace pin used for async mode
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\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
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\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
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\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
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\param[out] none
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\retval none
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*/
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void dbg_trace_pin_mode_set(uint32_t trace_mode)
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{
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DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
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DBG_CTL0 |= trace_mode;
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}
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