/*!
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\file drv_usbd_int.c
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\brief USB device mode interrupt routines
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\version 2020-08-01, V3.0.0, firmware for GD32F30x
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "usbd_conf.h"
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#include "drv_usbd_int.h"
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#include "usbd_transc.h"
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/* local function prototypes ('static') */
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static uint32_t usbd_int_epout (usb_core_driver *udev);
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static uint32_t usbd_int_epin (usb_core_driver *udev);
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static uint32_t usbd_int_rxfifo (usb_core_driver *udev);
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static uint32_t usbd_int_reset (usb_core_driver *udev);
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static uint32_t usbd_int_enumfinish (usb_core_driver *udev);
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static uint32_t usbd_int_suspend (usb_core_driver *udev);
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static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num);
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static const uint8_t USB_SPEED[4] = {
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[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_HIGH,
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[DSTAT_EM_FS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_FULL,
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[DSTAT_EM_FS_PHY_48MHZ] = (uint8_t)USB_SPEED_FULL,
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[DSTAT_EM_LS_PHY_6MHZ] = (uint8_t)USB_SPEED_LOW
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};
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/*!
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\brief USB device-mode interrupts global service routine handler
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval none
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*/
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void usbd_isr (usb_core_driver *udev)
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{
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if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) {
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uint32_t intr = udev->regs.gr->GINTF & udev->regs.gr->GINTEN;
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/* there are no interrupts, avoid spurious interrupt */
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if (!intr) {
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return;
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}
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/* OUT endpoints interrupts */
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if (intr & GINTF_OEPIF) {
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(void)usbd_int_epout (udev);
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}
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/* IN endpoints interrupts */
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if (intr & GINTF_IEPIF) {
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(void)usbd_int_epin (udev);
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}
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/* suspend interrupt */
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if (intr & GINTF_SP) {
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(void)usbd_int_suspend (udev);
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}
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/* wakeup interrupt */
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if (intr & GINTF_WKUPIF) {
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/* inform upper layer by the resume event */
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udev->dev.cur_status = USBD_CONFIGURED;
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/* clear interrupt */
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udev->regs.gr->GINTF = GINTF_WKUPIF;
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}
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/* start of frame interrupt */
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if (intr & GINTF_SOF) {
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if (udev->dev.class_core->SOF) {
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(void)udev->dev.class_core->SOF(udev);
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}
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/* clear interrupt */
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udev->regs.gr->GINTF = GINTF_SOF;
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}
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/* receive FIFO not empty interrupt */
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if (intr & GINTF_RXFNEIF) {
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(void)usbd_int_rxfifo (udev);
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}
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/* USB reset interrupt */
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if (intr & GINTF_RST) {
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(void)usbd_int_reset (udev);
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}
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/* enumeration has been done interrupt */
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if (intr & GINTF_ENUMFIF) {
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(void)usbd_int_enumfinish (udev);
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}
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/* incomplete synchronization IN transfer interrupt*/
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if (intr & GINTF_ISOINCIF) {
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if (NULL != udev->dev.class_core->incomplete_isoc_in) {
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(void)udev->dev.class_core->incomplete_isoc_in(udev);
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}
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/* Clear interrupt */
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udev->regs.gr->GINTF = GINTF_ISOINCIF;
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}
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/* incomplete synchronization OUT transfer interrupt*/
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if (intr & GINTF_ISOONCIF) {
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if (NULL != udev->dev.class_core->incomplete_isoc_out) {
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(void)udev->dev.class_core->incomplete_isoc_out(udev);
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}
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/* clear interrupt */
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udev->regs.gr->GINTF = GINTF_ISOONCIF;
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}
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#ifdef VBUS_SENSING_ENABLED
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/* Session request interrupt */
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if (intr & GINTF_SESIF) {
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udev->regs.gr->GINTF = GINTF_SESIF;
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}
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/* OTG mode interrupt */
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if (intr & GINTF_OTGIF) {
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if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) {
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}
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/* Clear OTG interrupt */
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udev->regs.gr->GINTF = GINTF_OTGIF;
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}
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#endif /* VBUS_SENSING_ENABLED */
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}
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}
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/*!
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\brief indicates that an OUT endpoint has a pending interrupt
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval operation status
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*/
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static uint32_t usbd_int_epout (usb_core_driver *udev)
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{
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uint32_t epintnum = 0U;
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uint8_t ep_num = 0U;
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for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) {
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if (epintnum & 0x01U) {
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__IO uint32_t oepintr = usb_oepintr_read (udev, ep_num);
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/* transfer complete interrupt */
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if (oepintr & DOEPINTF_TF) {
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/* clear the bit in DOEPINTF for this interrupt */
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udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF;
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if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
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__IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN;
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udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \
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(eplen & DEPLEN_TLEN);
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}
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/* inform upper layer: data ready */
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(void)usbd_out_transc (udev, ep_num);
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if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
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if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) {
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usb_ctlep_startout (udev);
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}
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}
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}
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/* setup phase finished interrupt (control endpoints) */
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if (oepintr & DOEPINTF_STPF) {
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/* inform the upper layer that a setup packet is available */
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(void)usbd_setup_transc (udev);
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udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF;
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}
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}
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}
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return 1U;
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}
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/*!
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\brief indicates that an IN endpoint has a pending interrupt
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval operation status
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*/
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static uint32_t usbd_int_epin (usb_core_driver *udev)
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{
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uint32_t epintnum = 0U;
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uint8_t ep_num = 0U;
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for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) {
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if (epintnum & 0x1U) {
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__IO uint32_t iepintr = usb_iepintr_read (udev, ep_num);
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if (iepintr & DIEPINTF_TF) {
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udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF;
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/* data transmission is completed */
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(void)usbd_in_transc (udev, ep_num);
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if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
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if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) {
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usb_ctlep_startout (udev);
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}
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}
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}
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if (iepintr & DIEPINTF_TXFE) {
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usbd_emptytxfifo_write (udev, (uint32_t)ep_num);
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udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE;
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}
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}
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}
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return 1U;
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}
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/*!
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\brief handle the RX status queue level interrupt
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval operation status
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*/
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static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
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{
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usb_transc *transc = NULL;
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uint8_t data_PID = 0U;
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uint32_t bcount = 0U;
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__IO uint32_t devrxstat = 0U;
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/* disable the Rx status queue non-empty interrupt */
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udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE;
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/* get the status from the top of the FIFO */
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devrxstat = udev->regs.gr->GRSTATP;
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uint8_t ep_num = (uint8_t)(devrxstat & GRSTATRP_EPNUM);
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transc = &udev->dev.transc_out[ep_num];
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bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U;
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data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U);
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switch ((devrxstat & GRSTATRP_RPCKST) >> 17U) {
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case RSTAT_GOUT_NAK:
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break;
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case RSTAT_DATA_UPDT:
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if (bcount > 0U) {
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(void)usb_rxfifo_read (&udev->regs, transc->xfer_buf, (uint16_t)bcount);
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transc->xfer_buf += bcount;
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transc->xfer_count += bcount;
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}
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break;
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case RSTAT_XFER_COMP:
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/* trigger the OUT endpoint interrupt */
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break;
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case RSTAT_SETUP_COMP:
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/* trigger the OUT endpoint interrupt */
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break;
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case RSTAT_SETUP_UPDT:
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if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) {
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/* copy the setup packet received in FIFO into the setup buffer in RAM */
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(void)usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount);
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transc->xfer_count += bcount;
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}
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break;
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default:
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break;
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}
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/* enable the Rx status queue level interrupt */
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udev->regs.gr->GINTEN |= GINTEN_RXFNEIE;
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return 1U;
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}
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/*!
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\brief handle USB reset interrupt
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval status
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*/
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static uint32_t usbd_int_reset (usb_core_driver *udev)
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{
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uint32_t i;
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/* clear the remote wakeup signaling */
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udev->regs.dr->DCTL &= ~DCTL_RWKUP;
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/* flush the Tx FIFO */
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(void)usb_txfifo_flush (&udev->regs, 0U);
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for (i = 0U; i < udev->bp.num_ep; i++) {
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udev->regs.er_in[i]->DIEPINTF = 0xFFU;
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udev->regs.er_out[i]->DOEPINTF = 0xFFU;
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}
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/* clear all pending device endpoint interrupts */
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udev->regs.dr->DAEPINT = 0xFFFFFFFFU;
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/* enable endpoint 0 interrupts */
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udev->regs.dr->DAEPINTEN = 1U | (1U << 16U);
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/* enable OUT endpoint interrupts */
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udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN;
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/* enable IN endpoint interrupts */
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udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN;
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/* reset device address */
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udev->regs.dr->DCFG &= ~DCFG_DAR;
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/* configure endpoint 0 to receive SETUP packets */
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usb_ctlep_startout (udev);
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/* clear USB reset interrupt */
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udev->regs.gr->GINTF = GINTF_RST;
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udev->dev.transc_out[0] = (usb_transc) {
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.ep_type = USB_EPTYPE_CTRL,
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.max_len = USB_FS_EP0_MAX_LEN
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};
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(void)usb_transc_active (udev, &udev->dev.transc_out[0]);
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udev->dev.transc_in[0] = (usb_transc) {
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.ep_addr = {
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.dir = 1U
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},
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.ep_type = USB_EPTYPE_CTRL,
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.max_len = USB_FS_EP0_MAX_LEN
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};
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(void)usb_transc_active (udev, &udev->dev.transc_in[0]);
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/* upon reset call user call back */
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udev->dev.cur_status = (uint8_t)USBD_DEFAULT;
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return 1U;
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}
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/*!
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\brief handle USB speed enumeration finish interrupt
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval status
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*/
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static uint32_t usbd_int_enumfinish (usb_core_driver *udev)
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{
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uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U);
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udev->regs.dr->DCTL &= ~DCTL_CGINAK;
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udev->regs.dr->DCTL |= DCTL_CGINAK;
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udev->regs.gr->GUSBCS &= ~GUSBCS_UTT;
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/* set USB turn-around time based on device speed and PHY interface */
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if (USB_SPEED[enum_speed] == (uint8_t)USB_SPEED_HIGH) {
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udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH;
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udev->regs.gr->GUSBCS |= 0x09U << 10U;
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} else {
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udev->bp.core_speed = (uint8_t)USB_SPEED_FULL;
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udev->regs.gr->GUSBCS |= 0x05U << 10U;
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}
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/* clear interrupt */
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udev->regs.gr->GINTF = GINTF_ENUMFIF;
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return 1U;
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}
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/*!
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\brief USB suspend interrupt handler
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval operation status
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*/
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static uint32_t usbd_int_suspend (usb_core_driver *udev)
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{
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__IO uint8_t low_power = udev->bp.low_power;
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__IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST);
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__IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)? 1U : 0U;
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udev->dev.backup_status = udev->dev.cur_status;
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udev->dev.cur_status = (uint8_t)USBD_SUSPENDED;
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if (low_power && suspend && is_configured) {
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/* switch-off the OTG clocks */
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*udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK;
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/* enter DEEP_SLEEP mode with LDO in low power mode */
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pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
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}
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/* clear interrupt */
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udev->regs.gr->GINTF = GINTF_SP;
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return 1U;
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}
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/*!
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\brief check FIFO for the next packet to be loaded
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\param[in] udev: pointer to USB device instance
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\param[in] ep_num: endpoint identifier which is in (0..3)
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\param[out] none
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\retval status
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*/
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static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num)
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{
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uint32_t len;
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uint32_t word_count;
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usb_transc *transc = &udev->dev.transc_in[ep_num];
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len = transc->xfer_len - transc->xfer_count;
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/* get the data length to write */
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if (len > transc->max_len) {
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len = transc->max_len;
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}
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word_count = (len + 3U) / 4U;
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while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \
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(transc->xfer_count < transc->xfer_len)) {
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len = transc->xfer_len - transc->xfer_count;
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if (len > transc->max_len) {
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len = transc->max_len;
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}
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/* write FIFO in word(4bytes) */
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word_count = (len + 3U) / 4U;
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/* write the FIFO */
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(void)usb_txfifo_write (&udev->regs, transc->xfer_buf, (uint8_t)ep_num, (uint16_t)len);
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transc->xfer_buf += len;
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transc->xfer_count += len;
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if (transc->xfer_count == transc->xfer_len) {
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/* disable the device endpoint FIFO empty interrupt */
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udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num);
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}
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}
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return 1U;
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}
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