/*!
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\file usbd_lld_core.c
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\brief USB device low level driver core
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\version 2020-08-01, V3.0.0, firmware for GD32F30x
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "usbd_lld_core.h"
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#include "usbd_enum.h"
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#define USB_EPTYPE_MASK 0x03U
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#if defined (__CC_ARM) /* ARM Compiler */
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static usbd_ep_ram btable_ep[EP_COUNT]__attribute__((at(USBD_RAM + 2 * (BTABLE_OFFSET & 0xFFF8))));
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#elif defined (__ICCARM__) /* IAR Compiler */
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__no_init usbd_ep_ram btable_ep[EP_COUNT] @(USBD_RAM + 2 * (BTABLE_OFFSET & 0xFFF8));
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#elif defined (__GNUC__) /* GNU GCC Compiler */
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usbd_ep_ram *btable_ep = (usbd_ep_ram *)(USBD_RAM + 2 * (BTABLE_OFFSET & 0xFFF8));
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#endif
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usb_core_drv usbd_core;
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static const uint32_t ep_type[] = {
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[USB_EP_ATTR_CTL] = EP_CONTROL,
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[USB_EP_ATTR_BULK] = EP_BULK,
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[USB_EP_ATTR_INT] = EP_INTERRUPT,
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[USB_EP_ATTR_ISO] = EP_ISO
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};
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/* local function prototypes ('static') */
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static void usbd_dp_pullup (FlagStatus status);
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static void usbd_core_reset (void);
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static void usbd_core_stop (void);
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static void usbd_address_set (usb_dev *udev);
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static void usbd_ep_reset (usb_dev *udev);
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static void usbd_ep_setup (usb_dev *udev, uint8_t buf_kind, uint32_t buf_addr, const usb_desc_ep *ep_desc);
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static void usbd_ep_rx_enable (usb_dev *udev, uint8_t ep_addr);
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static void usbd_ep_disable (usb_dev *udev, uint8_t ep_addr);
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static void usbd_ep_stall_set (usb_dev *udev, uint8_t ep_addr);
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static void usbd_ep_stall_clear (usb_dev *udev, uint8_t ep_addr);
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static void usbd_ep_data_write (uint8_t *user_fifo, uint8_t ep_num, uint16_t bytes);
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static uint16_t usbd_ep_data_read (uint8_t *user_fifo, uint8_t ep_num, uint8_t buf_kind);
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static void usbd_resume (usb_dev *udev);
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static void usbd_suspend (void);
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static void usbd_leave_suspend (void);
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static uint8_t usbd_ep_status (usb_dev *udev, uint8_t ep_addr);
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struct _usb_handler usbd_drv_handler = {
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.dp_pullup = usbd_dp_pullup,
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.init = usbd_core_reset,
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.deinit = usbd_core_stop,
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.suspend = usbd_suspend,
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.suspend_leave = usbd_leave_suspend,
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.resume = usbd_resume,
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.set_addr = usbd_address_set,
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.ep_reset = usbd_ep_reset,
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.ep_disable = usbd_ep_disable,
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.ep_setup = usbd_ep_setup,
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.ep_rx_enable = usbd_ep_rx_enable,
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.ep_write = usbd_ep_data_write,
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.ep_read = usbd_ep_data_read,
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.ep_stall_set = usbd_ep_stall_set,
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.ep_stall_clear = usbd_ep_stall_clear,
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.ep_status_get = usbd_ep_status
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};
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/*!
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\brief free buffer used from application by toggling the SW_BUF byte
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\param[in] ep_num: endpoint identifier (0..7)
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\param[in] dir: endpoint direction which can be OUT(0) or IN(1)
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\param[out] none
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\retval None
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*/
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void user_buffer_free (uint8_t ep_num, uint8_t dir)
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{
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if ((uint8_t)DBUF_EP_OUT == dir) {
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USBD_TX_DTG_TOGGLE(ep_num);
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} else if ((uint8_t)DBUF_EP_IN == dir) {
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USBD_RX_DTG_TOGGLE(ep_num);
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} else {
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/* no operation */
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}
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}
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/*!
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\brief set the status of pull-up pin
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\param[in] status: SET or RESET
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\param[out] none
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\retval none
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*/
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static void usbd_dp_pullup (FlagStatus status)
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{
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if (SET == status) {
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gpio_bit_set(USB_PULLUP, USB_PULLUP_PIN);
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} else {
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gpio_bit_reset(USB_PULLUP, USB_PULLUP_PIN);
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}
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}
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/*!
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\brief device core register initialization
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void usbd_core_reset (void)
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{
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/* reset the CLOSE bit */
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USBD_CTL = CTL_SETRST;
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/* may be need wait some time(tSTARTUP) */
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/* clear SETRST bit in USBD_CTL register */
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USBD_CTL = 0U;
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/* clear all pending interrupts */
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USBD_INTF = 0U;
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/* set descriptors table offset in USB dedicated SRAM */
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USBD_BADDR = BTABLE_OFFSET & 0xFFF8U;
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#ifdef LPM_ENABLED
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/* enable L1REQ interrupt */
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USBD_CTL = CTL_L1REQIE;
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USBD_LPMCS = LPMCS_LPMACK | LPMCS_LPMEN;
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#endif /* LPM_ENABLED */
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/* enable all interrupts mask bits */
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USBD_CTL |= CTL_STIE | CTL_WKUPIE | CTL_SPSIE | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE;
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}
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/*!
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\brief device core register configure when stop device
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void usbd_core_stop (void)
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{
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/* disable all interrupts and set USB reset */
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USBD_CTL = CTL_SETRST;
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/* clear all interrupt flags */
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USBD_INTF = 0U;
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/* close device */
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USBD_CTL = CTL_SETRST | CTL_CLOSE;
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}
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/*!
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\brief set device address
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval none
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*/
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static void usbd_address_set (usb_dev *udev)
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{
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USBD_DADDR = DADDR_USBEN | udev->dev_addr;
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}
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/*!
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\brief handle USB reset event
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\param[in] udev: pointer to USB device instance
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\param[out] none
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\retval none
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*/
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static void usbd_ep_reset (usb_dev *udev)
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{
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uint8_t i = 0U;
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usb_transc *transc = &udev->transc_in[0];
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btable_ep[0].tx_addr = EP0_TX_ADDR;
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btable_ep[0].tx_count = 0U;
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transc->max_len = USBD_EP0_MAX_SIZE;
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transc = &udev->transc_out[0];
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btable_ep[0].rx_addr = EP0_RX_ADDR;
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transc->max_len = USBD_EP0_MAX_SIZE;
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if (transc->max_len > 62U) {
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btable_ep[0].rx_count = ((uint16_t)((uint16_t)transc->max_len << 5) - 1U) | 0x8000U;
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} else {
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btable_ep[0].rx_count = ((transc->max_len + 1U) & ~1U) << 9U;
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}
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/* reset non-control endpoints */
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for (i = 1U; i < EP_COUNT; i++) {
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USBD_EPxCS(i) = (USBD_EPxCS(i) & EPCS_MASK) | i;
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}
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/* clear endpoint 0 register */
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USBD_EPxCS(0U)= (uint16_t)(USBD_EPxCS(0U));
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USBD_EPxCS(0U) = EP_CONTROL | EPRX_VALID | EPTX_NAK;
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/* set device address as default address 0 */
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USBD_DADDR = DADDR_USBEN;
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udev->cur_status = (uint8_t)USBD_DEFAULT;
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}
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/*!
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\brief endpoint initialization
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\param[in] udev: pointer to USB core instance
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\param[in] buf_kind: endpoint buffer kind
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\param[in] buf_addr: endpoint buffer address
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\param[in] ep_desc: pointer to endpoint descriptor
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\param[out] none
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\retval none
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*/
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static void usbd_ep_setup (usb_dev *udev, uint8_t buf_kind, uint32_t buf_addr, const usb_desc_ep *ep_desc)
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{
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uint8_t ep_addr = ep_desc->bEndpointAddress;
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uint8_t ep_num = EP_ID(ep_addr);
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uint16_t max_len = ep_desc->wMaxPacketSize;
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usb_transc *transc = NULL;
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/* set the endpoint type */
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USBD_EPxCS(ep_num) = ep_type[ep_desc->bmAttributes & USB_EPTYPE_MASK] | ep_num;
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if (EP_DIR(ep_addr)) {
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transc = &udev->transc_in[ep_num];
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transc->max_len = (uint8_t)max_len;
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if ((uint8_t)EP_BUF_SNG == buf_kind) {
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btable_ep[ep_num].tx_addr = buf_addr;
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/* configure the endpoint status as NAK status */
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USBD_EP_TX_STAT_SET(ep_num, EPTX_NAK);
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} else if ((uint8_t)EP_BUF_DBL == buf_kind) {
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USBD_EP_DBL_BUF_SET(ep_num);
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btable_ep[ep_num].tx_addr = buf_addr & 0xFFFFU;
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btable_ep[ep_num].rx_addr = (buf_addr & 0xFFFF0000U) >> 16U;
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USBD_EP_TX_STAT_SET(ep_num, EPTX_VALID);
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USBD_EP_RX_STAT_SET(ep_num, EPRX_DISABLED);
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} else {
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/* error operation */
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}
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} else {
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transc = &udev->transc_out[ep_num];
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transc->max_len = (uint8_t)max_len;
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if ((uint8_t)EP_BUF_SNG == buf_kind) {
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btable_ep[ep_num].rx_addr = buf_addr;
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} else if ((uint8_t)EP_BUF_DBL == buf_kind) {
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USBD_EP_DBL_BUF_SET(ep_num);
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USBD_TX_DTG_TOGGLE(ep_num);
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btable_ep[ep_num].tx_addr = buf_addr & 0xFFFFU;
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btable_ep[ep_num].rx_addr = (buf_addr & 0xFFFF0000U) >> 16U;
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if (max_len > 62U) {
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btable_ep[ep_num].tx_count = (((uint32_t)max_len << 5) - 1U) | 0x8000U;
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} else {
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btable_ep[ep_num].tx_count = ((max_len + 1U) & ~1U) << 9U;
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}
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} else {
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/* error operation */
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}
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if (max_len > 62U) {
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btable_ep[ep_num].rx_count = (((uint32_t)max_len << 5U) - 1U) | 0x8000U;
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} else {
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btable_ep[ep_num].rx_count = ((max_len + 1U) & ~1U) << 9U;
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}
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if ((uint8_t)EP_BUF_SNG == buf_kind) {
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/* configure the endpoint status as NAK status */
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USBD_EP_RX_STAT_SET(ep_num, EPRX_NAK);
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} else if ((uint8_t)EP_BUF_DBL == buf_kind) {
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USBD_EP_RX_STAT_SET(ep_num, EPRX_DISABLED);
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USBD_EP_TX_STAT_SET(ep_num, EPTX_NAK);
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} else {
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/* error operation */
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}
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}
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}
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/*!
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\brief configure the endpoint when it is disabled
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\param[in] udev: pointer to USB core instance
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\param[in] ep_addr: endpoint address
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in this parameter:
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bit0..bit6: endpoint number (0..7)
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bit7: endpoint direction which can be IN(1) or OUT(0)
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\param[out] none
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\retval none
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*/
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static void usbd_ep_disable (usb_dev *udev, uint8_t ep_addr)
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{
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(void)udev;
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uint8_t ep_num = EP_ID(ep_addr);
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if (EP_DIR(ep_addr)) {
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USBD_TX_DTG_CLEAR(ep_num);
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/* configure the endpoint status as DISABLED */
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USBD_EP_TX_STAT_SET(ep_num, EPTX_DISABLED);
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} else {
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USBD_RX_DTG_CLEAR(ep_num);
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/* configure the endpoint status as DISABLED */
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USBD_EP_RX_STAT_SET(ep_num, EPRX_DISABLED);
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}
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}
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/*!
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\brief enable endpoint to receive
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\param[in] udev: pointer to USB core instance
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\param[in] ep_addr: endpoint address
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in this parameter:
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bit0..bit6: endpoint number (0..7)
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bit7: endpoint direction which can be IN(1) or OUT(0)
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\param[out] none
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\retval none
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*/
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static void usbd_ep_rx_enable (usb_dev *udev, uint8_t ep_addr)
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{
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(void)udev;
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/* enable endpoint to receive */
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USBD_EP_RX_STAT_SET(EP_ID(ep_addr), EPRX_VALID);
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}
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/*!
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\brief set an endpoint to STALL status
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\param[in] udev: pointer to USB core instance
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\param[in] ep_addr: endpoint address
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in this parameter:
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bit0..bit6: endpoint number (0..7)
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bit7: endpoint direction which can be IN(1) or OUT(0)
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\param[out] none
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\retval none
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*/
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static void usbd_ep_stall_set (usb_dev *udev, uint8_t ep_addr)
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{
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uint8_t ep_num = EP_ID(ep_addr);
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if (0U == ep_num) {
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USBD_EP_TX_STAT_SET(0U, EPTX_STALL);
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USBD_EP_RX_STAT_SET(0U, EPRX_STALL);
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} else {
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if (EP_DIR(ep_addr)) {
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udev->transc_in[ep_num].ep_stall = 1U;
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USBD_EP_TX_STAT_SET(ep_num, EPTX_STALL);
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} else {
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udev->transc_out[ep_num].ep_stall = 1U;
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USBD_EP_RX_STAT_SET(ep_num, EPRX_STALL);
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}
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}
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}
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/*!
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\brief clear endpoint stalled status
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\param[in] udev: pointer to USB core instance
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\param[in] ep_addr: endpoint address
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in this parameter:
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bit0..bit6: endpoint number (0..7)
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bit7: endpoint direction which can be IN(1) or OUT(0)
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\param[out] none
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\retval none
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*/
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static void usbd_ep_stall_clear (usb_dev *udev, uint8_t ep_addr)
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{
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uint8_t ep_num = EP_ID(ep_addr);
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if (EP_DIR(ep_addr)) {
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/* clear endpoint data toggle bit */
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USBD_TX_DTG_CLEAR(ep_num);
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udev->transc_in[ep_num].ep_stall = 0U;
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/* clear endpoint stall status */
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USBD_EP_TX_STAT_SET(ep_num, EPTX_VALID);
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} else {
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/* clear endpoint data toggle bit */
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USBD_RX_DTG_CLEAR(ep_num);
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udev->transc_out[ep_num].ep_stall = 0U;
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/* clear endpoint stall status */
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USBD_EP_RX_STAT_SET(ep_num, EPRX_VALID);
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}
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}
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/*!
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\brief get the endpoint status
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\param[in] udev: pointer to USB core instance
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\param[in] ep_addr: endpoint address
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in this parameter:
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bit0..bit6: endpoint number (0..7)
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bit7: endpoint direction which can be IN(1) or OUT(0)
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\param[out] none
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\retval endpoint status
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*/
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static uint8_t usbd_ep_status (usb_dev *udev, uint8_t ep_addr)
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{
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(void)udev;
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uint32_t epcs = USBD_EPxCS(EP_ID(ep_addr));
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if (EP_DIR(ep_addr)) {
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return (uint8_t)(epcs & EPxCS_TX_STA);
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} else {
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return (uint8_t)(epcs & EPxCS_RX_STA);
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}
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}
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/*!
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\brief write data from user FIFO to USB RAM
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\param[in] user_fifo: pointer to user FIFO
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\param[in] ep_num: endpoint number
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\param[in] bytes: the bytes count of the write data
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\param[out] none
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\retval none
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*/
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static void usbd_ep_data_write (uint8_t *user_fifo, uint8_t ep_num, uint16_t bytes)
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{
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if (0U != bytes) {
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uint32_t n;
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uint32_t *write_addr = (uint32_t *)(btable_ep[ep_num].tx_addr * 2U + USBD_RAM);
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for (n = 0U; n < (bytes + 1U) / 2U; n++) {
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*write_addr++ = *((uint16_t*)user_fifo);
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user_fifo += 2U;
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}
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}
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btable_ep[ep_num].tx_count = bytes;
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USBD_EP_TX_STAT_SET(ep_num, EPTX_VALID);
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}
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/*!
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\brief read data from USBRAM to user FIFO
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\param[in] user_fifo: pointer to user FIFO
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\param[in] ep_num: endpoint number
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\param[in] buf_kind: endpoint buffer kind
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\param[out] none
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\retval none
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*/
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static uint16_t usbd_ep_data_read (uint8_t *user_fifo, uint8_t ep_num, uint8_t buf_kind)
|
{
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uint16_t n = 0U, bytes = 0U;
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uint32_t *read_addr = NULL;
|
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if ((uint8_t)EP_BUF_SNG == buf_kind) {
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bytes = (uint16_t)(btable_ep[ep_num].rx_count & EPRCNT_CNT);
|
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read_addr = (uint32_t *)(btable_ep[ep_num].rx_addr * 2U + USBD_RAM);
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} else if ((uint8_t)EP_BUF_DBL == buf_kind) {
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if (USBD_EPxCS(ep_num) & EPxCS_TX_DTG) {
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bytes = (uint16_t)(btable_ep[ep_num].tx_count & EPRCNT_CNT);
|
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read_addr = (uint32_t *)(btable_ep[ep_num].tx_addr * 2U + USBD_RAM);
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} else {
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bytes = (uint16_t)(btable_ep[ep_num].rx_count & EPRCNT_CNT);
|
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read_addr = (uint32_t *)(btable_ep[ep_num].rx_addr * 2U + USBD_RAM);
|
}
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} else {
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return 0U;
|
}
|
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for (n = 0U; n < (bytes + 1U) / 2U; n++) {
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*((uint16_t*)user_fifo) = (uint16_t)*read_addr++;
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user_fifo += 2U;
|
}
|
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return bytes;
|
}
|
|
#ifdef USBD_LOWPWR_MODE_ENABLE
|
|
/*!
|
\brief restore system clocks and power while exiting from suspend mode
|
\param[in] none
|
\param[out] none
|
\retval none
|
*/
|
static void lowpower_mode_exit (void)
|
{
|
/* restore system clock */
|
|
#ifdef LPM_ENABLED
|
/* enable IRC8M */
|
rcu_osci_on(RCU_IRC8M);
|
|
/* wait till IRC8M is ready */
|
while (RESET == rcu_flag_get(RCU_FLAG_IRC8MSTB)) {
|
}
|
#else
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/* enable HXTAL */
|
rcu_osci_on(RCU_HXTAL);
|
|
/* wait till HXTAL is ready */
|
while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB)) {
|
}
|
#endif
|
|
/* enable PLL */
|
rcu_osci_on(RCU_PLL_CK);
|
|
/* wait till PLL is ready */
|
while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB)) {
|
}
|
|
/* select PLL as system clock source */
|
rcu_system_clock_source_config(RCU_CKSYSSRC_PLL);
|
|
/* wait till PLL is used as system clock source */
|
while(0x08U != rcu_system_clock_source_get()) {
|
}
|
|
/* low power sleep on exit disabled */
|
system_lowpower_reset(SCB_LPM_DEEPSLEEP);
|
|
#ifdef USE_IRC48M
|
/* enable IRC48M clock */
|
rcu_osci_on(RCU_IRC48M);
|
|
/* wait till IRC48M is ready */
|
while (SUCCESS != rcu_osci_stab_wait(RCU_IRC48M)) {
|
}
|
|
rcu_ck48m_clock_config(RCU_CK48MSRC_IRC48M);
|
#endif
|
}
|
|
#endif /* USBD_LOWPWR_MODE_ENABLE */
|
|
/*!
|
\brief resume the USB device
|
\param[in] none
|
\param[out] none
|
\retval none
|
*/
|
static void usbd_resume (usb_dev *udev)
|
{
|
#ifdef LPM_ENABLED
|
if(1 == udev->lpm.L1_remote_wakeup){
|
USBD_CTL |= CTL_L1RSREQ;
|
}
|
#endif /* LPM_ENABLED */
|
|
if(1U == usbd_core.dev->pm.remote_wakeup){
|
/* make USB resume */
|
USBD_CTL |= CTL_RSREQ;
|
}
|
}
|
|
/*!
|
\brief set USB device to leave mode
|
\param[in] none
|
\param[out] none
|
\retval none
|
*/
|
static void usbd_leave_suspend (void)
|
{
|
/* clear low_power mode bit in USBD_CTL */
|
USBD_CTL &= ~CTL_LOWM;
|
|
#ifdef USBD_LOWPWR_MODE_ENABLE
|
|
/* restore normal operations */
|
lowpower_mode_exit();
|
|
#endif /* USBD_LOWPWR_MODE_ENABLE */
|
|
/* clear SETSPS bit */
|
USBD_CTL &= ~CTL_SETSPS;
|
}
|
|
/*!
|
\brief set USB device to enter suspend mode
|
\param[in] none
|
\param[out] none
|
\retval none
|
*/
|
static void usbd_suspend (void)
|
{
|
/* set USB module to suspend and low-power mode */
|
USBD_CTL |= CTL_SETSPS | CTL_LOWM;
|
|
#ifdef USBD_LOWPWR_MODE_ENABLE
|
|
/* check wakeup flag is set */
|
if (0U == (USBD_INTF & INTF_WKUPIF)) {
|
/* enter DEEP_SLEEP mode with LDO in low power mode */
|
pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
|
} else {
|
/* clear wakeup interrupt flag */
|
CLR(WKUPIF);
|
|
/* clear set_suspend flag */
|
USBD_CTL &= ~CTL_SETSPS;
|
}
|
|
#endif /* USBD_LOWPWR_MODE_ENABLE */
|
}
|
