;/*!
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; \file startup_gd32f30x_xd.s
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; \brief start up file
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;
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; \version 2017-02-10, V1.0.0, firmware for GD32F30x
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; \version 2018-10-10, V1.1.0, firmware for GD32F30x
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; \version 2018-12-25, V2.0.0, firmware for GD32F30x
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; \version 2020-09-30, V2.1.0, firmware for GD32F30x
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;*/
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;
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;/*
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; Copyright (c) 2020, GigaDevice Semiconductor Inc.
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; Redistribution and use in source and binary forms, with or without modification,
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;are permitted provided that the following conditions are met:
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;
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; 1. Redistributions of source code must retain the above copyright notice, this
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; list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright notice,
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; this list of conditions and the following disclaimer in the documentation
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; and/or other materials provided with the distribution.
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; 3. Neither the name of the copyright holder nor the names of its contributors
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; may be used to endorse or promote products derived from this software without
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; specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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;OF SUCH DAMAGE.
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000400
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; /* reset Vector Mapped to at Address 0 */
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; /* external interrupts handler */
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DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
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DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
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DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
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DCD RTC_IRQHandler ; 19:RTC through EXTI Line
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DCD FMC_IRQHandler ; 20:FMC
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DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
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DCD EXTI0_IRQHandler ; 22:EXTI Line 0
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DCD EXTI1_IRQHandler ; 23:EXTI Line 1
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DCD EXTI2_IRQHandler ; 24:EXTI Line 2
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DCD EXTI3_IRQHandler ; 25:EXTI Line 3
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DCD EXTI4_IRQHandler ; 26:EXTI Line 4
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DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
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DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
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DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
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DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
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DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
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DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
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DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
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DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
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DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD HP and CAN0 TX
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DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD LP and CAN0 RX0
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DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
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DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
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DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
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DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
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DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
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DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
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DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
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DCD TIMER1_IRQHandler ; 44:TIMER1
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DCD TIMER2_IRQHandler ; 45:TIMER2
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DCD TIMER3_IRQHandler ; 46:TIMER3
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DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
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DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
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DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
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DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
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DCD SPI0_IRQHandler ; 51:SPI0
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DCD SPI1_IRQHandler ; 52:SPI1
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DCD USART0_IRQHandler ; 53:USART0
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DCD USART1_IRQHandler ; 54:USART1
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DCD USART2_IRQHandler ; 55:USART2
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DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
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DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
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DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
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DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
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DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
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DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
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DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
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DCD ADC2_IRQHandler ; 63:ADC2
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DCD EXMC_IRQHandler ; 64:EXMC
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DCD SDIO_IRQHandler ; 65:SDIO
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DCD TIMER4_IRQHandler ; 66:TIMER4
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DCD SPI2_IRQHandler ; 67:SPI2
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DCD UART3_IRQHandler ; 68:UART3
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DCD UART4_IRQHandler ; 69:UART4
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DCD TIMER5_IRQHandler ; 70:TIMER5
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DCD TIMER6_IRQHandler ; 71:TIMER6
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DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
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DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
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DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
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DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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;/* reset Handler */
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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;/* dummy Exception Handlers */
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler\
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PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler\
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PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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; /* external interrupts handler */
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EXPORT WWDGT_IRQHandler [WEAK]
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EXPORT LVD_IRQHandler [WEAK]
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EXPORT TAMPER_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT RCU_CTC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA0_Channel0_IRQHandler [WEAK]
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EXPORT DMA0_Channel1_IRQHandler [WEAK]
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EXPORT DMA0_Channel2_IRQHandler [WEAK]
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EXPORT DMA0_Channel3_IRQHandler [WEAK]
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EXPORT DMA0_Channel4_IRQHandler [WEAK]
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EXPORT DMA0_Channel5_IRQHandler [WEAK]
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EXPORT DMA0_Channel6_IRQHandler [WEAK]
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EXPORT ADC0_1_IRQHandler [WEAK]
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EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
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EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
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EXPORT CAN0_RX1_IRQHandler [WEAK]
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EXPORT CAN0_EWMC_IRQHandler [WEAK]
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EXPORT EXTI5_9_IRQHandler [WEAK]
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EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
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EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
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EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
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EXPORT TIMER0_Channel_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT TIMER3_IRQHandler [WEAK]
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EXPORT I2C0_EV_IRQHandler [WEAK]
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EXPORT I2C0_ER_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT USART0_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT EXTI10_15_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT USBD_WKUP_IRQHandler [WEAK]
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EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
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EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
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EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
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EXPORT TIMER7_Channel_IRQHandler [WEAK]
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EXPORT ADC2_IRQHandler [WEAK]
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EXPORT EXMC_IRQHandler [WEAK]
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EXPORT SDIO_IRQHandler [WEAK]
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EXPORT TIMER4_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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EXPORT TIMER5_IRQHandler [WEAK]
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EXPORT TIMER6_IRQHandler [WEAK]
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EXPORT DMA1_Channel0_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_IRQHandler [WEAK]
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EXPORT DMA1_Channel2_IRQHandler [WEAK]
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EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
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;/* external interrupts handler */
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WWDGT_IRQHandler
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LVD_IRQHandler
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TAMPER_IRQHandler
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RTC_IRQHandler
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FMC_IRQHandler
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RCU_CTC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA0_Channel0_IRQHandler
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DMA0_Channel1_IRQHandler
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DMA0_Channel2_IRQHandler
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DMA0_Channel3_IRQHandler
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DMA0_Channel4_IRQHandler
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DMA0_Channel5_IRQHandler
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DMA0_Channel6_IRQHandler
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ADC0_1_IRQHandler
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USBD_HP_CAN0_TX_IRQHandler
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USBD_LP_CAN0_RX0_IRQHandler
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CAN0_RX1_IRQHandler
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CAN0_EWMC_IRQHandler
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EXTI5_9_IRQHandler
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TIMER0_BRK_TIMER8_IRQHandler
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TIMER0_UP_TIMER9_IRQHandler
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TIMER0_TRG_CMT_TIMER10_IRQHandler
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TIMER0_Channel_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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TIMER3_IRQHandler
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I2C0_EV_IRQHandler
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I2C0_ER_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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SPI0_IRQHandler
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SPI1_IRQHandler
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USART0_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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EXTI10_15_IRQHandler
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RTC_Alarm_IRQHandler
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USBD_WKUP_IRQHandler
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TIMER7_BRK_TIMER11_IRQHandler
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TIMER7_UP_TIMER12_IRQHandler
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TIMER7_TRG_CMT_TIMER13_IRQHandler
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TIMER7_Channel_IRQHandler
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ADC2_IRQHandler
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EXMC_IRQHandler
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SDIO_IRQHandler
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TIMER4_IRQHandler
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SPI2_IRQHandler
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UART3_IRQHandler
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UART4_IRQHandler
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TIMER5_IRQHandler
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TIMER6_IRQHandler
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DMA1_Channel0_IRQHandler
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DMA1_Channel1_IRQHandler
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DMA1_Channel2_IRQHandler
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DMA1_Channel3_4_IRQHandler
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B .
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ENDP
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ALIGN
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; user Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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